DisassemblerArm.h

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/* Disassembly specific to the ARM architecture. */

#ifndef ROSE_DISASSEMBLER_ARM_H
#define ROSE_DISASSEMBLER_ARM_H

class DisassemblerArm: public Disassembler {
public:
    DisassemblerArm()
        : decodeUnconditionalInstructions(true), ip(0), insn(0), cond(arm_cond_unknown) {
        init();
    }

    DisassemblerArm(const DisassemblerArm& other)
        : Disassembler(other), decodeUnconditionalInstructions(other.decodeUnconditionalInstructions), 
          ip(other.ip), insn(other.insn), cond(other.cond) {
    }

    virtual ~DisassemblerArm() {}

    virtual Disassembler *clone() const {
        return new DisassemblerArm(*this);
    }

    virtual bool can_disassemble(SgAsmGenericHeader*) const;

    virtual SgAsmInstruction *disassembleOne(const MemoryMap *map, rose_addr_t start_va, AddressSet *successors=NULL);

    virtual void assembleOne(SgAsmInstruction*, SgUnsignedCharList&) {abort();}

    virtual SgAsmInstruction *make_unknown_instruction(const Exception&);

private:
    class ExceptionArm: public Exception {
    public:
        ExceptionArm(const std::string &mesg, const DisassemblerArm *d, size_t bit=0)
            : Exception(mesg, d->ip) {
            /* Convert four-byte instruction to little-endian buffer. FIXME: assumes little-endian ARM system */
            bytes.push_back(d->insn & 0xff);
            bytes.push_back((d->insn>>8) & 0xff);
            bytes.push_back((d->insn>>16) & 0xff);
            bytes.push_back((d->insn>>24) & 0xff);
            this->bit = bit;
        }
    };

    static SgAsmArmInstruction *makeInstructionWithoutOperands(uint32_t address, const std::string& mnemonic, int condPos,
                                                               ArmInstructionKind kind, ArmInstructionCondition cond,
                                                               uint32_t insn);
    SgAsmArmRegisterReferenceExpression *makeRegister(uint8_t reg) const;
    SgAsmArmRegisterReferenceExpression *makePsrFields(bool useSPSR, uint8_t fields) const;
    SgAsmArmRegisterReferenceExpression *makePsr(bool useSPSR) const;

    SgAsmExpression *makeRotatedImmediate() const;
    SgAsmExpression *makeShifterField() const; 
    SgAsmArmInstruction *makeDataProcInstruction(uint8_t opcode, bool s, SgAsmExpression* rn, SgAsmExpression* rd,
                                                 SgAsmExpression* rhsOperand);
    SgAsmDoubleWordValueExpression *makeSplit8bitOffset() const;
    SgAsmDoubleWordValueExpression *makeBranchTarget() const;
    SgAsmExpression *decodeMemoryAddress(SgAsmExpression* rn) const;
    SgAsmArmInstruction *decodeMediaInstruction() const;
    SgAsmArmInstruction *decodeMultiplyInstruction() const;
    SgAsmArmInstruction *decodeExtraLoadStores() const;
    SgAsmArmInstruction *decodeMiscInstruction() const;
    SgAsmArmInstruction *disassemble();
    
    void init();

    void startInstruction(rose_addr_t start_va, uint32_t c) {
        ip = start_va;
        insn = c;
        cond = arm_cond_unknown;
    }

    /* Per-instruction data members (mostly set by startInstruction()) */
    bool decodeUnconditionalInstructions;       
    uint32_t ip;                                
    uint32_t insn;                              
    ArmInstructionCondition cond;
};

#endif

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