1 #ifndef ROSE_BinaryAnalysis_Disassembler_Base_H
2 #define ROSE_BinaryAnalysis_Disassembler_Base_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
6 #include <Rose/BinaryAnalysis/CallingConvention.h>
7 #include <Rose/BinaryAnalysis/Disassembler/BasicTypes.h>
8 #include <Rose/BinaryAnalysis/Disassembler/Exception.h>
9 #include <Rose/BinaryAnalysis/InstructionSemantics/BaseSemantics.h>
10 #include <Rose/BinaryAnalysis/MemoryMap.h>
11 #include <Rose/BinaryAnalysis/Unparser/Settings.h>
12 #include <Rose/Diagnostics.h>
14 #include "integerOps.h"
17 #include <boost/serialization/access.hpp>
18 #include <boost/serialization/string.hpp>
19 #include <boost/serialization/version.hpp>
27 namespace BinaryAnalysis {
28 namespace Disassembler {
84 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
86 friend class boost::serialization::access;
89 void serialize(S &s,
const unsigned version) {
90 s & BOOST_SERIALIZATION_NVP(p_registers);
91 s & BOOST_SERIALIZATION_NVP(REG_IP);
92 s & BOOST_SERIALIZATION_NVP(REG_SS);
94 s & BOOST_SERIALIZATION_NVP(REG_SF);
95 s & BOOST_SERIALIZATION_NVP(p_byteOrder);
96 s & BOOST_SERIALIZATION_NVP(p_wordSizeBytes);
97 s & BOOST_SERIALIZATION_NVP(p_name);
99 s & BOOST_SERIALIZATION_NVP(instructionAlignment_);
128 const std::string&
name()
const {
131 void name(
const std::string &s) {
139 virtual Ptr
clone()
const = 0;
156 void byteOrder(ByteOrder::Endianness sex) { p_byteOrder = sex; }
201 ASSERT_forbid(REG_IP.
isEmpty());
207 ASSERT_forbid(REG_SP.
isEmpty());
size_t instructionAlignment() const
Property: Instruction alignment requirement.
virtual bool canDisassemble(SgAsmGenericHeader *) const =0
Predicate determining the suitability of a disassembler for a specific file header.
static SgAsmInstruction * find_instruction_containing(const InstructionMap &insns, rose_addr_t va)
Finds the highest-address instruction that contains the byte at the specified virtual address...
virtual RegisterDescriptor instructionPointerRegister() const
Returns the register that points to instructions.
virtual Unparser::BasePtr unparser() const =0
Unparser.
Base class for machine instructions.
void wordSizeBytes(size_t nbytes)
Property: Basic word size in bytes.
virtual Ptr clone() const =0
Creates a new copy of a disassembler.
RegisterDescriptor REG_LINK
Register descriptors initialized during construction.
RegisterDictionaryPtr p_registers
Description of registers available for this platform.
InstructionSemantics::BaseSemantics::DispatcherPtr p_proto_dispatcher
Prototypical dispatcher for creating real dispatchers.
void registerDictionary(const RegisterDictionaryPtr &rdict)
Properties: Register dictionary.
AddressSet get_block_successors(const InstructionMap &, bool &complete)
Calculates the successor addresses of a basic block and adds them to a successors set...
const CallingConvention::Dictionary & callingConventions() const
Property: Calling convention dictionary.
Main namespace for the ROSE library.
ByteOrder::Endianness byteOrder() const
Property: Byte order of instructions in memory.
void callingConventions(const CallingConvention::Dictionary &d)
Properties: Register dictionary.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
CallingConvention::Dictionary & callingConventions()
Properties: Register dictionary.
size_t instructionAlignment_
Positive alignment constraint for instruction addresses.
std::vector< Definition::Ptr > Dictionary
A ordered collection of calling convention definitions.
Describes (part of) a physical CPU register.
virtual RegisterDescriptor stackPointerRegister() const
Returns the register that points to the stack.
size_t p_wordSizeBytes
Basic word size in bytes.
virtual RegisterDescriptor stackFrameRegister() const
Returns the register that ponts to the stack frame.
size_t wordSizeBytes() const
Property: Basic word size in bytes.
ByteOrder::Endianness p_byteOrder
Byte order of instructions in memory.
virtual RegisterDescriptor stackSegmentRegister() const
Returns the segment register for accessing the stack.
void mark_referenced_instructions(SgAsmInterpretation *, const MemoryMap::Ptr &, const InstructionMap &)
Marks parts of the file that correspond to instructions as having been referenced.
Base class for reference counted objects.
void byteOrder(ByteOrder::Endianness sex)
Property: Byte order of instructions in memory.
virtual SgAsmInstruction * makeUnknownInstruction(const Exception &)=0
Makes an unknown instruction from an exception.
virtual RegisterDescriptor callReturnRegister() const
Returns the register that holds the return address for a function.
const std::string & name() const
Property: Name by which disassembler is registered.
const Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::DispatcherPtr & dispatcher() const
Return an instruction semantics dispatcher if possible.
std::string p_name
Name by which this dissassembler is registered.
Exception thrown by the disassemblers.
Sawyer::SharedPointer< Base > BasePtr
Reference counted pointer for disassemblers.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &map, rose_addr_t start_va, AddressSet *successors=NULL)=0
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
bool isEmpty() const
Predicate returns true if the width is zero.
RegisterDictionaryPtr registerDictionary() const
Properties: Register dictionary.
Represents an interpretation of a binary container.
Map< rose_addr_t, SgAsmInstruction * > InstructionMap
The InstructionMap is a mapping from (absolute) virtual address to disassembled instruction.
Virtual base class for instruction disassemblers.
void name(const std::string &s)
Property: Name by which disassembler is registered.