ROSE  0.11.145.0
DispatcherPowerpc.h
1 // Semantics for 32-bit Motorola-IBM PowerPC microprocessors using ROSE instruction semantics API2
2 // This code was derived from $ROSE/projects/assemblyToSourceAst/powerpcInstructionSemantics.h,
3 // which is mostly a copy of $ROSE/projects/SemanticSignatureVectors/powerpcInstructionSemantics.h
4 //
5 // The ROSE style guide indicates that PowerPC, when used as part of a symbol in ROSE source code,
6 // should be capitalized as "Powerpc" (e.g., "DispatcherPowerpc", the same rule that consistently
7 // capitializes x86 as "DispatcherX86").
8 #ifndef ROSE_BinaryAnalysis_InstructionSemantics_DispatcherPowerpc_H
9 #define ROSE_BinaryAnalysis_InstructionSemantics_DispatcherPowerpc_H
10 #include <featureTests.h>
11 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
12 
13 #include <Rose/BinaryAnalysis/BasicTypes.h>
14 #include <Rose/BinaryAnalysis/InstructionSemantics/BaseSemantics.h>
15 
16 #include <boost/serialization/access.hpp>
17 #include <boost/serialization/base_object.hpp>
18 #include <boost/serialization/export.hpp>
19 #include <boost/serialization/split_member.hpp>
20 
21 namespace Rose {
22 namespace BinaryAnalysis {
23 namespace InstructionSemantics {
24 
26 typedef boost::shared_ptr<class DispatcherPowerpc> DispatcherPowerpcPtr;
27 
29 public:
32 
35 
46 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
47 private:
48  friend class boost::serialization::access;
49 
50  template<class S>
51  void save(S &s, const unsigned /*version*/) const {
52  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
53  }
54 
55  template<class S>
56  void load(S &s, const unsigned /*version*/) {
57  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
58  regcache_init();
59  iproc_init();
60  memory_init();
61  }
62 
63  BOOST_SERIALIZATION_SPLIT_MEMBER();
64 #endif
65 
66 protected:
67  // Prototypical constructor
68  DispatcherPowerpc();
69 
70  // Prototypical constructor
71  DispatcherPowerpc(size_t addrWidth, const RegisterDictionaryPtr &regs/*=NULL*/);
72 
73  DispatcherPowerpc(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionaryPtr &regs);
74 
75 public:
76  ~DispatcherPowerpc();
77 
78 private:
80  void iproc_init();
81 
85  void regcache_init();
86 
88  void memory_init();
89 
90 public:
93  static DispatcherPowerpcPtr instance();
94 
96  static DispatcherPowerpcPtr instance(size_t addrWidth, const RegisterDictionaryPtr&);
97 
99  static DispatcherPowerpcPtr instance(const BaseSemantics::RiscOperatorsPtr&, size_t addrWidth,
100  const RegisterDictionaryPtr&);
101 
103  virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &, size_t addrWidth,
104  const RegisterDictionaryPtr&) const override;
105 
107  static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr&);
108 
109  virtual void set_register_dictionary(const RegisterDictionaryPtr&) override;
110 
111  virtual RegisterDescriptor instructionPointerRegister() const override;
112  virtual RegisterDescriptor stackPointerRegister() const override;
113  virtual RegisterDescriptor stackFrameRegister() const override;
114  virtual RegisterDescriptor callReturnRegister() const override;
115 
116  virtual int iprocKey(SgAsmInstruction *insn_) const override {
117  SgAsmPowerpcInstruction *insn = isSgAsmPowerpcInstruction(insn_);
118  assert(insn!=NULL);
119  return insn->get_kind();
120  }
121 
126  void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow);
127 
129  virtual void updateCr0(const BaseSemantics::SValuePtr &result);
130 
134 
139 };
140 
141 } // namespace
142 } // namespace
143 } // namespace
144 
145 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
147 #endif
148 
149 #endif
150 #endif
boost::shared_ptr< class DispatcherPowerpc > DispatcherPowerpcPtr
Shared-ownership pointer to a PowerPC instruction dispatcher.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
Base class for machine instructions.
void writeAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *destination, const BaseSemantics::SValuePtr &value)
Writes a value to a memory address and updates a register with the effective address to which the val...
virtual void updateCr0(const BaseSemantics::SValuePtr &result)
Write status flags for result.
Main namespace for the ROSE library.
virtual RegisterDescriptor stackFrameRegister() const override
Returns the stack call frame register.
virtual int iprocKey(SgAsmInstruction *insn_) const override
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
Dispatches instructions through the RISC layer.
Definition: Dispatcher.h:43
Describes (part of) a physical CPU register.
Rose::BinaryAnalysis::PowerpcInstructionKind const & get_kind() const
Property: Instruction kind.
Represents one PowerPC machine instruction.
static DispatcherPowerpcPtr instance()
Construct a prototypical dispatcher.
virtual RegisterDescriptor callReturnRegister() const override
Returns the function call return address register.
virtual RegisterDescriptor stackPointerRegister() const override
Returns the stack pointer register.
Base class for expressions.
static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &)
Dynamic cast to a DispatcherPowerpcPtr with assertion.
BaseSemantics::SValuePtr readAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *, size_t valueNBits)
Reads from a memory address and updates a register with the effective address that was read...
void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow)
Set the XER OV and SO bits as specified.
Base class for most instruction semantics RISC operators.
Definition: RiscOperators.h:49
DispatcherPowerpcPtr Ptr
Shared-ownership pointer.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &, size_t addrWidth, const RegisterDictionaryPtr &) const override
Virtual constructor.
virtual RegisterDescriptor instructionPointerRegister() const override
Returns the instruction pointer register.