8 #ifndef ROSE_BinaryAnalysis_InstructionSemantics_DispatcherPowerpc_H
9 #define ROSE_BinaryAnalysis_InstructionSemantics_DispatcherPowerpc_H
10 #include <featureTests.h>
11 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
13 #include <Rose/BinaryAnalysis/BasicTypes.h>
14 #include <Rose/BinaryAnalysis/InstructionSemantics/BaseSemantics.h>
16 #include <boost/serialization/access.hpp>
17 #include <boost/serialization/base_object.hpp>
18 #include <boost/serialization/export.hpp>
19 #include <boost/serialization/split_member.hpp>
22 namespace BinaryAnalysis {
23 namespace InstructionSemantics {
46 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
48 friend class boost::serialization::access;
51 void save(S &s,
const unsigned )
const {
52 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(
Super);
56 void load(S &s,
const unsigned ) {
57 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(
Super);
63 BOOST_SERIALIZATION_SPLIT_MEMBER();
93 static DispatcherPowerpcPtr
instance();
145 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
boost::shared_ptr< class DispatcherPowerpc > DispatcherPowerpcPtr
Shared-ownership pointer to a PowerPC instruction dispatcher.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
Base class for machine instructions.
RegisterDescriptor REG_XER_OV
Cached register.
void writeAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *destination, const BaseSemantics::SValuePtr &value)
Writes a value to a memory address and updates a register with the effective address to which the val...
virtual void updateCr0(const BaseSemantics::SValuePtr &result)
Write status flags for result.
RegisterDescriptor REG_CR0_LT
Cached register.
Main namespace for the ROSE library.
virtual RegisterDescriptor stackFrameRegister() const override
Returns the stack call frame register.
RegisterDescriptor REG_XER_CA
Cached register.
virtual int iprocKey(SgAsmInstruction *insn_) const override
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
Dispatches instructions through the RISC layer.
RegisterDescriptor REG_IAR
Cached register.
Describes (part of) a physical CPU register.
Rose::BinaryAnalysis::PowerpcInstructionKind const & get_kind() const
Property: Instruction kind.
Represents one PowerPC machine instruction.
static DispatcherPowerpcPtr instance()
Construct a prototypical dispatcher.
virtual RegisterDescriptor callReturnRegister() const override
Returns the function call return address register.
RegisterDescriptor REG_CR0
Cached register.
virtual RegisterDescriptor stackPointerRegister() const override
Returns the stack pointer register.
RegisterDescriptor REG_XER_SO
Cached register.
BaseSemantics::Dispatcher Super
Base type.
Base class for expressions.
static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &)
Dynamic cast to a DispatcherPowerpcPtr with assertion.
RegisterDescriptor REG_LR
Cached register.
RegisterDescriptor REG_CR
Cached register.
BaseSemantics::SValuePtr readAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *, size_t valueNBits)
Reads from a memory address and updates a register with the effective address that was read...
void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow)
Set the XER OV and SO bits as specified.
Base class for most instruction semantics RISC operators.
DispatcherPowerpcPtr Ptr
Shared-ownership pointer.
RegisterDescriptor REG_XER
Cached register.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &, size_t addrWidth, const RegisterDictionaryPtr &) const override
Virtual constructor.
virtual RegisterDescriptor instructionPointerRegister() const override
Returns the instruction pointer register.
RegisterDescriptor REG_CTR
Cached register.